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div (fp32)@divagr1925·Collected 4d ago

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X discussion: an indie developer compiles an NPU into Qwen3.5-4B weights and runs Karpathy's stories260K, an LLM inside an LLM

A widely discussed experiment on X: on Oct 31 indie developer div (@divagr1925) showed QwenPU, which compiles a 32-bit RISC-V CPU plus a vector unit directly into the weights of Qwen3.5-4B and runs Andrej Karpathy's 260K-parameter stories260K inside the model's own forward passes, matching a reference implementation token for token. None of the added weights are trained; a compiler computes them all. The post drew about 1,540 likes, 163 reposts and 85K views and became an X trending story. It is a personal, self-described work-in-progress project: the checkpoint is 26.7 GB and one story token takes about 16 seconds on an L4. This is a write-up of the discussion, not an official announcement from any company.

Key Takeaways

Buzz: the @divagr1925 post has about 1,540 likes, 163 reposts, 71 quotes and 85K views (public X metrics as of Nov 1); the earlier Qwenputer post (Oct 28) has about 5,880 likes and was quote-posted by Shopify CEO Tobi Lutke
Method: 13 compiled computer layers (RV32IM + Zba + a bignum unit + the vector unit) sit in front of Qwen's 32 layers, widening the hidden size from 2560 to 5120 while Qwen's own weights stay unchanged (GitHub README)
Efficiency: trace tokens per story token drop from 2.43M for plain C to 53K; at about 3,300 trace tokens per second on an L4, one story token takes about 16 seconds (author-reported)
Verification: the story program runs free on a GPU executor for all 3,184,920 steps, checked against a reference CPU model at every step, which the author says is exact; no independent reproduction has been published yet
Open source: code is MIT and weights are Apache-2.0 as a modified Qwen3.5-4B, on Hugging Face and ModelScope; the 26.7 GB checkpoint needs a 40 GB or larger GPU

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Linked Models & Agents:

⚡ Qwen3.5-4B⚡ stories260K🌐 Alibaba Qwen

#X discussion#Qwen#QwenPU#Qwenputer#in-weights computing#RISC-V#Karpathy#open source

Anthropic@AnthropicAI·Collected 13d ago

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Anthropic Frontier Red Team: Claude, working with Theorem, formally proved no-crash properties at the RISC-V assembly level for 239 entry points across 123 OSS-Fuzz libraries, about 180M lines of Rocq

On 2026-10-22 Anthropic’s Frontier Red Team, working with Theorem, published research in which Claude turned OSS-Fuzz fuzz tests into formal specs and proved on the compiled RISC-V binaries that no input under 64 MB causes a crash. Over a few weeks it proved 239 entry points across 123 libraries, about 180 million lines of Rocq checked by the Rocq kernel. Along the way it found and patched hundreds of bugs, including an out-of-bounds write that needed a roughly 20 MB input with a rare layout. Anthropic says Opus 5.5 needs about 40% fewer tokens than Opus 5 to finish proofs.

Key Takeaways

Scale: 239 entry points across 123 OSS-Fuzz libraries, about 180M lines of Rocq, a typical proof about 600,000 lines for binaries with a median of 18,000 RISC-V instructions
Scope: no crash (including ASan memory errors and failed assertions) for any input under 64 MB, assuming a single-threaded static RISC-V binary on Linux with musl
Hundreds of bugs found while proving, including an out-of-bounds write that needed about a 20 MB input, plus a rediscovery of CVE-2026-56132 in libexpat
On 36 small verification tasks Opus 5.5 proves half with about 40% fewer tokens than Opus 5; a shared proof workspace cut tokens a further 17% (Anthropic figures)
A subset of proofs and the RISC-V and Linux semantics are public (theorem-labs/oss-verify-proofs), and Theorem published a Claude skill to help developers start

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Linked Models & Agents:

⚡ Claude Opus 5.5 ⚡ Claude Opus 5 🤖 Claude 🌐 Anthropic 🌐 Theorem 🌐 Google

#formal verification#Rocq#RISC-V#OSS-Fuzz#AddressSanitizer#memory safety#Security#Frontier Red Team

FeSensFeSens·Collected 29d ago

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openTPU, an open-source AI accelerator developed by AI agents, goes viral: full RTL/ISA/compiler stack runs Qwen3.5, Gemma 4 and a 35B MoE on a Kintex-7 FPGA card at up to 85.8 tok/s

FeSens/openTPU (Apache-2.0) hit the Hacker News front page (250+ points, 300+ comments). Reusing the AI-driven method from auto-arch-tournament (AI-designed RISC-V cores), the author had AI agents iterate on an inference accelerator; one repo holds SystemVerilog RTL, the ISA, a bit-exact simulator, a kernel language/compiler and a profiler. On a Kintex-7 xc7k480t PCIe card it runs Qwen3, Qwen3.5, Gemma 4, Phi-4-mini and others with real weights, token-for-token identical to the simulator; LFM2.5-230M decodes at 85.8 tok/s in 4-bit and Qwen3.5-35B-A3B reaches 3.95 tok/s with host-streamed experts.

Key Takeaways

Full stack in one repo: SystemVerilog RTL, 8x32-bit-word ISA, bit-exact Python simulator, @ol.jit kernel compiler and Lens profiler, Apache-2.0 (GitHub)
Measured device decode (4-bit, int8 head): LFM2.5-230M 85.8 tok/s, Qwen3-0.6B 31.3, Qwen3.5-2B 12.09, Gemma 4 E2B 12.14 tok/s
Uses 82-94% of the 17.1 GB/s DDR3-1066 peak while decoding; 133.33 MHz clock, four-column systolic array
MoE offload: Qwen3.5-35B-A3B at 3.95 tok/s (153 MB of experts streamed per token, 62% slot hit), LFM2.5-8B-A1B at 10.6 tok/s (offload docs)
4-bit weights (FP4 with two-level block scales, 4.25 bits/weight) decode 40-45% faster than int8, with per-model perplexity cost documented

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Linked Models & Agents:

⚡ Qwen3.5⚡ Gemma 4⚡ LFM2.5⚡ Phi-4 Mini

#Opentpu#AI accelerator#Fpga#Open hardware#AI designed hardware#Systemverilog#Edge inference#Hacker news